module reg_files (
    input clk,
    input rst,
    input reg_write,
    input [4:0] rs1, rs2, rd,
    input [31:0] write_data,
    output [31:0] read_data1,
    output [31:0] read_data2
);

  reg [31:0] regs[31:0];

  integer i;
  initial regs[0] = 32'b0;
  // always @(posedge clk, posedge rst) begin
  always @(negedge clk, posedge rst) begin
    if(rst) begin
      for(i=1; i<32; i=i+1)
        regs[i] <= 0;
    end
    else
      if(reg_write && (rd != 5'b0))
        regs[rd] <= write_data;
  end

  assign read_data1 = (rs1 != 0) ? regs[rs1] : 32'b0;
  assign read_data2 = (rs2 != 0) ? regs[rs2] : 32'b0;

endmodule